Information about integrated circuit path delay may be utilized to specify proper supply voltage settings to conserve energy, while still providing sufficient supply voltage to meet performance requirements. As the size of metal oxide semiconductor (MOS) transistors decreases, delay of the integrated circuit paths and clock frequencies have become more sensitive to transient variations in supply voltage and temperature. The decrease in size of MOS transistors has also led to a decrease in supply voltages provided to the integrated circuits. For example, for a 32/28 nm complementary metal oxide semiconductor (CMOS) technology node, the supply voltage, VDD, may be about 1V and for a 22/20 nm CMOS technology node, VDD may be about 0.9V. The supply voltage of integrated circuits is typically provided by a supply voltage regulator, which can be integrated on the same die as the integrated circuits or on a separate die.
The supply voltage required by an integrated circuit may change due to on/off cycles of subsystems of a computing device, clock frequency changes, and workload changes, such as changes in the applications executed using the integrated circuit. These types of supply voltage changes are intended to optimize power dissipation of integrated circuits. The intended change of the supply voltage, which is usually initiated by the operating system executed on the integrated circuit, is known as dynamic voltage scaling or adaptive voltage scaling. The supply voltage changes initiated by the operating system may optimize the energy dissipation of the integrated circuit by adapting the clock frequency to the actual, time-varying performance requirement of a specific application.
Supply voltage changes may also be caused by total transient current variations of the integrated circuit. These unintended total current variations may be referred to as IR-drop, since the total current variation is translated into a total variation of the on-die power supply voltage. To illustrate, the supply voltage variation, ΔV, is approximately given by the product of the total variation of the current, ΔI, and the total resistance of the sum of all wires connecting the power supply voltage regulator to the power supply pins of the integrated circuit, RSUM. The supply voltage changes due to the total transient current variations may be up to 20% of the nominal, specified supply voltage.
As the supply voltage for integrated circuits decreases, the delay sensitivity to variations in supply voltage increases. For example, unintended changes in the supply voltage required by an integrated circuit may occur faster than a supply voltage regulator can adapt the supply voltage to the changes. In other words the transient response of the supply voltage regulator may be slower than the time scale of an on-chip IR drop event. Thus, the supply voltage required by the integrated circuit may not be readily available causing a delay in the execution of processes by the integrated circuit. In addition, uncertainty in measuring the delay of integrated circuit paths may be introduced because the supply voltage regulator is not able to keep up with the changes in the supply voltage required by the integrated circuit.
Uncertainty in measuring delay of integrated circuit paths may result in difficulty determining whether the status of a chip is critical (e.g. that a timing violation is occurring or is imminent). A timing violation may be defined as a status where the delay of a speed critical path of an integrated circuit exceeds the clock period of the integrated circuit. A timing violation can lead to a temporal or permanent malfunction of the integrated circuit.
In a particular example, the delay of a speed critical path of pipelined integrated circuits comprising clock controlled flip-flops or registers separated by combinational logic having about 10-50 CMOS logic stages, may have several components. To illustrate, the delay of a speed critical path of a pipelined integrated circuit may include the clock to output delay of a first data launching flip flop, the delay of the combinational logic, a setup time of a second data launching flip flop, and a timing margin to cover non-idealities in clock distribution, such as clock skew and jitter. Any spatial and/or temporal variation of these timing parameters of the pipelined integrated circuit may produce a timing violation. In this disclosure, clock skew may include a spatial variation of the arrival time of the clock edge at different flip-flops due to imbalances in the clock distribution circuitry and clock jitter may include a transient variation of the arrival time of the clock edge at different flip flops.
Timing violations in integrated circuits may be also generated by unintended temperature variations. These temperature variations may be caused by heating of the silicon substrate due to the power dissipation of the integrated circuit. Temperature variations may also be produced by placing additional power dissipating integrated circuits on the same printed circuit board as a particular integrated circuit or placing the additional power dissipating integrated circuits and the particular integrated circuit within one package, such that the heat generated by the additional power dissipating integrated circuits diffuses to the particular integrated circuit and increases the temperature. Temperature variations may occur on a much slower time scale than unintended voltage variations. For example, temperature variations vary between several millisecond and seconds, whereas unintended supply voltage variations occur between 100 picoseconds and about 10 milliseconds.
In CMOS technologies, both the temperature and the supply voltage variation may alter the speed of the MOS transistors. For example, at supply voltages above 1.1V in a 32/28 nm CMOS technology, increasing temperatures reduce the drive current of MOS transistors and hence reduce the speed of the CMOS circuits. In another example, at supply voltages below 0.9V in a 32/28 nm CMOS technology, increasing temperature increases the drive current of MOS transistors and hence increases the speed of the CMOS circuits. The interactions of temperature and supply voltage variations are a priori not fully known during the design phase of CMOS circuit design. Therefore, safety margins may be added to the target circuit speed. In addition, to provide error free or substantially error free functionality of integrated circuits for a large number of possible temperature and supply voltage states, simulations assuming distinct supply voltage and temperature operating points may be performed during the design phase.